1. Field of the Invention
The present invention relates to frame synchronization data transmission, and in particular to a circuit for detecting an error in a synchronizing signal.
2. Description of the Related Art
In frame synchronization data transmission, the frame is made up of a plurality of subframes, and a frame synchronizing signal, which represents a start of the frame of the data signal, is assigned to the starting or first subframe with a code of a specified pattern. In order to punctuate, if required, the remaining part of the frame, a subframe synchronizing signal of a predetermined logic level is assigned to a specified bit, say the kth bit, of each subframe. The kth bit is normally the first bit.
FIG. 1 shows a conventional frame format of data signal S3, enable signal S1 and clock pulse signal S2 in the frame synchronization data transmission. In the figure, one frame is made up of a plurality of subframes, each subframe having 8 bits, each bit being transmitted in synchronization with clock pulse signal S2. Hereafter, each subframe with 8 bits is referred to as an octet or an OCT. Enable signal S1 makes logic 1 only when a datum is present. A code made up of octadic Os is assigned to the starting octet as the frame synchronizing signal. The subframe or octet synchronizing signal is not designated in the frame format shown in FIG. 1.
FIG. 2 shows another frame format, where an octet synchronizing signal is designated. The synchronizing signal is assigned to the first bit of each octet and designated with the logic 1. Hereafter, the frame synchronizing signal and the subframe synchronizing signal are referred to as the FRM SYN and the SBFRM SYN, respectively, and the two SYNs are referred to in general as the SYN.
FIG. 3 shows a data transmission system, in which a circuit for detecting an FRM SYN is used. Hereafter the circuit for detecting an FRM SYN is referred to as the FRM SYN detecting circuit. In the transmitting end, a digital data signal sent from a transmitting terminal is converted to an analog data signal by means of digital-analog converter 91. The analog data signal is then transmitted through transmitting antenna 92, received by receiving antenna 93 and supplied to analog-digital converter 94 to be converted to a digital data signal. FRM SYN detecting circuit 95 detects an FRM SYN from the digital data signal in order to distinguish whether the digital data signal is a frame of the transmitted data signal, or a data signal which involves any other information, and then sends the digital data signal to a receiving terminal.
In actual cases the FRM SYN detecting circuit is provided in the transmitting end as well in order to check any possible change in the data signal caused by noise.
FIG. 4 shows a block diagram of a typical prior art SYN detecting circuit. The circuit is composed of serial-parallel converter 10, memory 12 and CPU 13. Serial-parallel converter 10, enabled by enable signal S1, receives serial data signal S3, and converts serial data signal S3 to parallel data signal S11 in synchronization with clock pulse signal S2. Parallel data signal S11 is first stored in memory 12. After all the data signals transmitted by the data transmission concerned are stored, CPU 13 detects the SYN by means of software.
A problem encountered in the SYN detecting circuit described above is that, since all the serial-to-parallel-converted data have to be once stored in the memory in order to check the bits assigned to the SYN, it takes a long time to detect them.